The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to integrated circuits and methods for receiving data.
As the speed of data busses used in computing, packet processing and other digital electronics applications increases, problems arising from skew and/or jitter of various signals tend to increase. For example, in synchronous data bus applications, skew and/or jitter of bits of a data bus and/or between bits of the data bus and the bus clock signal can cause errors in transferring data between a source device and a destination device coupled by the bus. Skew may be attributable to differences between data lines within the source device chip, between data lines within the source device packaging (e.g., lead frame), between data lines of the bus itself, between data lines of the destination device packaging, and/or between data lines in the destination device chip. Jitter may be attributable to noise sources coupling into the data lines.
Skew and/or jitter can be reduced by careful design of the devices and/or interconnecting wiring. However, this may require multiple IC and/or board design iterations and/or may preclude the use of IC and/or board layouts that may be desirable for other functional reasons. Moreover, the amount of freedom in varying an IC design tends to be limited, as it is generally desirable that a particular IC be usable in a variety of different board layouts. Accordingly there is a need for integrated circuits and operating methods which can provide improved design flexibility and efficiency while reducing signal jitter and skew effects.